The present invention relates to the fabrication of a semiconductor device. More specifically, the present invention relates to a method of fabricating a semiconductor device that includes a first region containing CMOS logic devices and a second region containing a fieldless array of memory transistors.
In many memory applications, memory transistors and conventional CMOS devices are fabricated on a single semiconductor wafer. Typically, the CMOS devices are fabricated in a first region of the wafer, while the memory transistors are fabricated in a second region of the wafer. On some wafers, the memory transistors are fabricated as part of a fieldless array. A fieldless array is defined as an array that does not use field oxide to isolate the various elements of the array. Because field oxide is not required to isolate the memory transistors in a fieldless array, the memory transistors can be laid out with a relatively high density.
In certain applications, conventional CMOS devices (e.g., transistors) are fabricated in the second region, but do not form part of the fieldless array. That is, the CMOS devices located in the second region are isolated by field oxide. Thus, the second region can include both memory transistors and CMOS devices.
In order to distinguish the above-described transistors, the following nomenclature will be used. As used herein, the term xe2x80x9clogic transistorxe2x80x9d refers to a transistor fabricated in accordance with conventional CMOS processes, regardless of whether the transistor is fabricated in the first region or the second region of the semiconductor wafer. A CMOS logic transistor is isolated from other elements by field oxide. CMOS logic transistors can further be classified as high voltage CMOS logic transistors and low voltage CMOS logic transistors. High voltage CMOS logic transistors have a thicker gate oxide than low voltage CMOS logic transistors, thereby enabling the high voltage CMOS logic transistors to withstand higher gate voltages. The term xe2x80x9cfieldless array transistorxe2x80x9d refers to a floating gate type non-volatile memory transistor that is used to form a fieldless array. A fieldless array transistor does not require field oxide isolation.
The process steps required to fabricate high and low voltage CMOS logic transistors are not fully compatible with the process steps required to fabricate fieldless array transistors. As a result, relatively complex processes would be required to form the high and low voltage CMOS logic transistors and the fieldless array transistors on the same wafer. It would therefore be desirable to have an efficient process for fabricating high and low voltage CMOS logic transistors and fieldless array transistors on the same wafer.
Accordingly, the present invention provides efficient processes for fabricating high voltage CMOS logic transistors, low voltage CMOS logic transistors and fieldless array transistors on the same wafer.
In accordance with one embodiment, the fieldless array transistors are fabricated by forming a first dielectric layer over a semiconductor substrate, forming a floating gate layer over the first dielectric layer, and then forming a second dielectric layer over the floating gate layer. The floating gate layer and/or the interfaces between the floating gate layer and the first and second dielectric layers function as a charge storage or charge trapping region. In a particular embodiment, the first and second dielectric layers are silicon oxide, and the floating gate layer is silicon nitride, thereby forming an oxide-nitride-oxide (ONO) structure. A mask having a plurality of openings is formed over the second dielectric layer. The openings in the mask define locations in the substrate that will be used to form diffusion bit lines, as well as source and drain regions, of the fieldless array transistors. These locations are referred to as bit line regions.
A first impurity is implanted through the openings of the mask into the bit line regions of the substrate. The first impurity passes through the second dielectric layer, the floating gate layer, and the first dielectric layer before reaching the substrate. In a particular embodiment, the first impurity is implanted at a first angle and then a second angle with respect to the upper surface of the substrate. For example, the first impurity can be implanted at angles of 65 degrees and 115 degrees. Under these conditions, the first impurity is implanted in the substrate at locations beneath the mask. The first impurity has a first conductivity type (e.g., p-type).
The second dielectric layer and the floating gate layer are etched through the openings of the mask. In accordance with one embodiment, the second dielectric layer (and a portion of the floating gate layer) are etched by a low pressure isotropic plasma enhanced etch in a vacuum chamber using only a flourocarbon gas, such as CF4. The second dielectric layer is removed by a plasma assisted isotropic etch that uses a gas mixture of SF6 and HBr in the same vacuum chamber. A second impurity can then be implanted through the openings of the mask at an angle of about 90 degrees with respect to the upper surface of the substrate. The second impurity is implanted into the bit line regions of the substrate. The second impurity has a second conductivity type, opposite the first conductivity type (e.g., n-type).
The mask is removed, and an oxidation step is subsequently performed. The oxidation step results in the formation of bit line oxide regions at the locations where the second dielectric layer and the floating gate layer were previously etched (i.e., over the bit line regions). Floating gate structures, which include the first dielectric layer, the floating gate layer and the second dielectric layer, are formed at the locations where the second dielectric layer and the floating gate layer were not previously etched.
The oxidation step activates the first impurity and the second impurity in the substrate (with subsequent high temperature steps completing the activation). In general, the first impurity adjusts the threshold voltages of the fieldless array transistors. The second impurity forms the diffusion bit line conductors, as well as the source and drain regions, of the fieldless array transistors. A plurality of gate electrodes are formed over the bit line oxide regions and the floating gate structures, thereby completing the fieldless array transistors. The bit line oxide isolates the diffusion bit line conductors from the gate electrodes.
In accordance with another aspect of the present invention, high voltage and low voltage CMOS transistors are fabricated on the same wafer as the fieldless array using an efficient series of process steps. In a particular embodiment, the low voltage transistors are fabricated in a first region of the substrate and the high voltage transistors are fabricated in a second region of the substrate. A first ion implant is initially performed in both the first and second regions. The first ion implant is selected to adjust the threshold voltages of the high voltage transistors in the desired manner. In one embodiment, the first ion implant is performed through the above-mentioned ONO structure.
The ONO structure is removed in the first and second regions and a first gate oxide is then formed over both the first and second regions of the semiconductor substrate. A second ion implant is then performed into only the first region of the substrate. The first region therefore receives both the first and second ion implants. The combination of the first and second ion implants adjusts the threshold voltages of the low voltage transistors in the desired manner.
The first gate oxide is then removed from first region of the substrate. A second gate oxide is then formed over both the first and second regions of the substrate. The second gate oxide forms the gate oxide layer for the low voltage transistors in the first region. In the second region, the second gate oxide combines with the previously formed first gate oxide to form the gate oxide layer for the high voltage transistors in the second region.
The above-described process steps advantageously enable high voltage CMOS transistors, low voltage CMOS transistors and fieldless array transistors to be fabricated on the same wafer in an efficient manner. The present invention will be more fully understood in view of the following description and drawings.